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w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 1 - revision f 1m-bit, 2m-bit, 4m-bit and 8m-bit serial flash memory with 4kb sectors and dual output spi
w25x10a, w25x20a, w25x40a, w25x80a - 2 - table of contents 1. ......................................................................................................... 4 general description 2. ................................................................................................................................. 4 features 3. ....................................................................................... 5 pin configuration soic 150-mil 4. ....................................................................................... 5 pin configuration soic 208-mil 5. ....................................................................................... 5 pin configuration pdip 300-mil 6. .................................................................................. 6 pad configuration wson 6x5-mm 7. ..................................................................................................................... 6 pin description 7.1 ............................................................................................................... 7 package types 7.2 ............................................................................................................ 7 chip select (/cs) 7.3 ................................................................................................. 7 serial data output (do) 7.4 ......................................................................................................... 7 write protect (/wp) 7.5 ............................................................................................................... 7 hold (/hold) 7.6 .......................................................................................................... 7 serial clock (clk) 7.7 ..................................................................................... 7 serial data input / output (dio) 8. ...................................................................................................................... 8 block diagram 9. ................................................................................................... 9 functional description 9.1 ......................................................................................................... 9 spi operations 9.1.1 ........................................................................................................................9 spi modes 9.1.2 ...............................................................................................................9 dual output spi 9.1.3 ...................................................................................................................9 hold function 9.2 .................................................................................................. 10 write protection 9.2.1 ....................................................................................................10 write protect features 10. ................................................................................... 11 control and status registers 10.1 .................................................................................................... 11 status register 10.1.1 ............................................................................................................................11 busy 10.1.2 ............................................................................................11 write enable latch (wel) 10.1.3 ..............................................................................11 block protect bits (bp2, bp1, bp0) 10.1.4 .....................................................................................11 top/bottom block protect (tb) 10.1.5 ...............................................................................................................11 reserved bits 10.1.6 ......................................................................................12 status register protect (srp) 10.1.7 ..............................................................................13 status register memory protection 10.2 ........................................................................................................... 14 instructions 10.2.1 ........................................................................14 manufacturer and devi ce identification 10.2.2 ..............................................................................................................15 instruction set 10.2.3 ........................................................................................................16 write enable (06h) 10.2.4 .......................................................................................................16 write disable (04h) 10.2.5 ..........................................................................................17 read status register (05h) 10.2.6 ..........................................................................................18 write status register (01h)
w25x10a, w25x20a, w25x40a, w25x80a ...........................................................................................................19 publ ication release date: august 7, 2009 - 3 - revision f 10.2.7 read data (03h) 10.2.8 ...........................................................................................................20 fast read (0bh) 10.2.9 .......................................................................................21 fast read dual output (3bh) 10.2.10 ...................................................................................................22 page program (02h) 10.2.11 .....................................................................................................23 sector erase (20h) 10.2.12 ......................................................................................................24 block erase (d8h) 10.2.13 .............................................................................................25 chip erase (c7h or 60h) 10.2.14 ......................................................................................................26 power-down (b9h) 10.2.15 .....................................................................27 release power-down / device id (abh) 10.2.16 .........................................................................29 read manufacturer / device id (90h) 10.2.17 .........................................................................................................30 jedec id (9fh) 11. ......................................................................................... 31 electrical characteristics 11.1 .......................................................................................... 31 absolute maximum ratings 11.2 ......................................................................................................... 31 operating ranges 11.3 .............................................................. 31 power-up timing and write inhibit threshold 11.4 ........................................................................................ 33 dc electrical characteristics 11.5 ........................................................................................ 34 ac measurement conditions 11.6 ........................................................................................ 35 ac electrical characteristics 11.7 ........................................................................... 36 ac electrical characteristics (cont?d) 11.8 ..................................................................................................... 37 serial output timing 11.9 .................................................................................................................. 37 input timing 11.10 ................................................................................................................. 37 hold timing 12. .................................................................................................... 38 package specification 12.1 ...................................................................... 38 8-pin soic 150-mil (package code sn) 12.2 ...................................................................... 39 8-pin soic 208-mil (package code ss) 12.3 ...................................................................... 40 8-pin pdip 300-mil (package code da) 12.4 ............................................................ 41 8-contact 6x5mm wson (package code zp) 8-pad wson 6x5mm cont?d. ................................................................................................... 42 13. .................................................................................................... 43 ordering information 13.1 .................................................................. 44 valid part numbers and top side marking 14. ................................................................................................................ 45 revision history
w25x10a, w25x20a, w25x40a, w25x80a - 4 - 1. general description the w25x10a (1m-bit), w25x20a (2m-bit), w25x40a (4m-bit) and w25x80a (8m-bit) serial flash memories provide a storage solution for systems wi th limited space, pins and power. the 25x series offers flexibility and performance well beyond ordinary serial flash devices. they are ideal for code download applications as well as storing voice, text and data. the devices operate on a single 2.7v to 3.6v power supply with current consumption as low as 5ma active and 1a for power-down. all devices are offered in space-saving packages. the w25x10a/20a/40a/80a array is organi zed into 512/1024/2048/4096 programmable pages of 256-bytes each. up to 256 bytes can be programmed at a time using the page program instruction. pages can be erased in groups of 16 (sector erase) , groups of 256 (block erase) or the entire chip (chip erase). the w25x10a/20a /40a/80a has 32/64/128/256 erasabl e sectors and 2/4/8/16 erasable blocks respectively. the small 4kb sectors allow for greater flexibility in applications that require data and parameter storage. (see figure 2.) the w25x10a/20a/40a/80a supports the standard serial peripheral interface (spi), and a high performance dual output spi using four pins: serial clock, chip select, serial data i/o and serial data out. spi clock frequencies of up to 100mhz ar e supported allowing equivalent clock rates of 200mhz when using the fast read dual output inst ruction. these transfer rates are comparable to those of 8 and 16-bit parallel flash memories. a hold pin, write protect pin and programmable wr ite protect, with top or bottom array control features, provide further control flexibility. additionally, the devic e supports jedec standard manufacturer and device identification. 2. features ? family of serial flash memories ? w25x10a: 1m-bit / 128k-byte (131,072) ? w25x20a: 2m-bit / 256k-byte (262,144) ? w25x40a: 4m-bit / 512k-byte (524,288) ? w25x80a: 8m-bit / 1m-byte (1,048,576) ? 256-bytes per programmable page ? unif orm 4k-byte sectors / 64k-byte blocks ? spi with single or dual outputs ? clock, chip select, data i/o, data out ? optional hold function for spi flexibility ? data transfer up to 200m-bits / second ? clock operation to 100mhz ? fast read dual output instruction ? auto-increment read capability ? softw are and hardware write protection ? write-protect all or portion of memory ? enable/disable protection with /wp pin ? top or bottom array protection ? flexible architecture w ith 4kb sectors ? sector erase (4k-bytes) ? block erase (64k-byte) ? page program up to 256 bytes <2ms ? more than 100,000 erase/write cycles ? more than 20-year data retention ? low power consumption, wide temperature range ? single 2.7 to 3.6v supply ? 5ma active current, 1a power-down (typ) ? -40 to +85c operating range ? space efficient packaging ? 8-pin soic 150-mil (1) ? 8-pin soic 208-mil (w25x40a/80a) ? 8-pin pdip 300-mil ? 8-pad wson 6x5-mm . note 1: see ?valid part number and top side marking? section, note 2 for special ordering information.
w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 5 - revision f 3. pin configuration soic 150-mil figure 1a. w25x10a, w25x20a, w25x 40a and w25x80a pin assignments, 8-pin soic (package code sn) 4. pin configuration soic 208-mil figure 1b. w25x40a and w25x80a pin assi gnments, 8-pin soic (package code ss) 5. pin configuration pdip 300-mil figure 1c. w25x40a and w25x80a pin assi gnments, 8-pin pdip (package code da)
w25x10a, w25x20a, w25x40a, w25x80a - 6 - 6. pad configuration wson 6x5-mm figure 1d. w25x10a, w25x20a, w25x 40a and w25x80a pad assignments, 8-pad wson (package code zp) 7. pin description soic 150-mil, soic 208-mil, pd ip 300-mil, and wson 6x5-mm pin no. pin name i/o function 1 /cs i chip select input 2 do o data output 3 /wp i write protect input 4 gnd ground 5 dio i/o data input / output 6 clk i serial clock input 7 /hold i hold input 8 vcc power supply
w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 7 - revision f 7.1 package types all parts are offered in an 8-pin plas tic 150-mil width soic (package code sn) (1) as shown in figure 1a and the 8-pad 6x5-mm wson (package code zp) as shown in figure 1c, and 1d respectively. the w25x40a and w25x80a are offered in both the 8-pi n plastic 208-mil width soic (package code ss) as shown in figure 1b and the 8-pin 300-mil dip (package code da). package diagrams and dimensions are illustrated at the end of this datasheet. 7.2 chip select (/cs) the spi chip select (/cs) pin enables and disables device operation. when /cs is high the device is deselected and the serial data output (do) pin is at high impedance. when deselected, the devices power consumption will be at standby levels unless an in ternal erase, program or status register cycle is in progress. when /cs is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. after power-up, /cs must transition from high to low before a new inst ruction will be accepted. the /cs input must track the vcc supply level at power-up (see ?write protection? and figure 20). if needed a pull-up resister on /cs can be used to accomplish this. 7.3 serial data output (do) the spi serial data output (do) pin provides a means for data and status to be serially read from (shifted out of) the device. data is shifted out on the falling edge of the serial clock (clk) input pin. 7.4 write protect (/wp) the write protect (/wp) pin can be used to prevent the status register from being written. used in conjunction with the status register?s block pr otect (bp2, bp1, and bp0) bits and status register protect (srp) bit, a portion or the entire memory array can be hardware protected. the /wp pin is active low. 7.5 hold (/hold) the hold (/hold) pin allows the device to be paused while it is actively selected. when /hold is brought low, while /cs is low, the do pin will be at hi gh impedance and signals on the dio and clk pins will be ignored (don?t care). when /hold is brought high, device operation can resume. the /hold function can be useful when multiple devices are sharing the same spi signals. (?see hold function?) 7.6 serial clock (clk) the spi serial clock input (clk) pin provides the timing for serial input and output operations. (?see spi operations?) 7.7 serial data input / output (dio) the spi serial data input/output (dio) pin provi des a means for instructions, addresses and data to be serially written to (shifted in to) the device. data is latched on the rising edge of the serial clock (clk) input pin. the dio pin is also used as an out put when the fast read dual output instruction is executed. note 1: see ?valid part number and top side marking? section, note 2 for special ordering information.
w25x10a, w25x20a, w25x40a, w25x80a - 8 - 8. block diagram figure 2. w25x10a, w25x20a, w25x 40a and w25x80a block diagram
w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 9 - revision f 9. functional description 9.1 spi operations 9.1.1 spi modes the w25x10a/20a/40a/80a is accessed through an spi compatible bus consisting of four signals: serial clock (clk), chip select (/cs), serial data input/output (dio) and serial data output (do). both spi bus operation modes 0 (0,0) and 3 (1,1 ) are supported. the primary difference between mode 0 and mode 3 concerns the normal state of t he clk signal when the spi bus master is in standby and data is not being transferred to the serial flash. for mode 0 the clk signal is normally low. for mode 3 the clk signal is normally high. in either case data input on the dio pin is sampled on the rising edge of the clk. data on the do and dio pins are clocked out on the falling edge of clk. 9.1.2 dual output spi the w25x10a/20a/40a/80a supports dual output operation when using the ?fast read with dual output? (3b hex) instruction. this feature allows data to be transferred from the serial flash memory at twice the rate possible with the standard spi. th is instruction is ideal for quickly downloading code from flash to ram upon power-up (code-shadowing) or for applications that cache code-segments to ram for execution. the dual output feature simply allows the spi input pin to also serve as an output during this instruction. all other operations use the standard spi interface with single output signal. 9.1.3 hold function the /hold signal allows the w25x10a/20a/40a/80a operation to be paused while it is actively selected (when /cs is low). the /hold function may be useful in cases where the spi data and clock signals are shared with other devices. for example, consider if the page buffer was only partially written when a priority interrupt requires use of the spi bus. in this case the /hold function can save the state of the instruction and t he data in the buffer so programming can resume where it left off once the bus is available again. to initiate a /hold condition, the device must be selected with /cs low. a /hold condition will activate on the falling edge of the /hold signal if t he clk signal is already low. if the clk is not already low the /hold condition will activate after the next falling edge of clk. the /hold condition will terminate on the rising edge of the /hold signal if the clk signal is already low. if the clk is not already low the /hold condition will terminate after the next falling edge of clk. during a /hold condition, the serial data output (d o) is high impedance, and serial data input/output (dio) and serial clock (clk) are ignor ed. the chip select (/cs) signal should be kept active (low) for the full duration of the /hold operation to avoid resetting the internal logic state of the device.
w25x10a, w25x20a, w25x40a, w25x80a - 10 - 9.2 write protection applications that use non-volatile memory must ta ke into consideration the possibility of noise and other adverse system conditions that may compromi se data integrity. to address this concern the w25x10a/20a/40a/80a provides several means to protect dat a from inadvertent writes. 9.2.1 write protect features ? device resets when vcc is below threshold. ? time delay write disable after power-up. ? write enable/disable instructions. ? automatic write disable after program and erase. ? software write protection using status register. ? hardware write protection using status register and /wp pin. ? write protection using power-down instruction. upon power-up or at power-down the w25x10a/20a/ 40a/80a will maintain a reset condition while vcc is below the threshold value of v wi , (see power-up timing and voltage levels and figure 20). while reset, all operations are disabled and no instru ctions are recognized. during power-up and after the vcc voltage exceeds v wi , all program and erase related instructions are further disabled for a time delay of t puw . this includes the write enable, page progr am, sector erase, block erase, chip erase and the write status register instructions. note that the chip select pin (/cs) must track the vcc supply level at power-up until the vcc-min level and t vsl time delay is reached. if needed a pull- up resister on /cs can be used to accomplish this. after power-up the device is automatically placed in a write-disabled state with the status register write enable latch (wel) set to a 0. a write enable instruction must be issued before a page program, sector erase, chip erase or write stat us register instruction will be accepted. after completing a program, erase or write instruction the write enable latch (we l) is automatically cleared to a write-disabled state of 0. software controlled write protection is facilitated using the write stat us register instruction and setting the status register protect (srp) and block pr otect (tb, bp2, bp1, and bp0) bits. these status register bits allow a portion or all of the memory to be configured as read only. used in conjunction with the write protect (/wp) pin, changes to t he status register can be enabled or disabled under hardware control. see status regi ster for further information. additionally, the power-down instruction offers an extra level of write protection as all instructions are ignored except for the releas e power-down instruction.
w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 11 - revision f 10. control and status registers the read status register instruction can be used to provide status on the av ailability of the flash memory array, if the device is write enabled or dis abled, and the state of writ e protection. the write status register instruction can be used to configure the device write protecti on features. see figure 3. 10.1 status register 10.1.1 busy busy is a read only bit in the status register (s0) t hat is set to a 1 state w hen the device is executing a page program, sector erase, block erase, chip er ase or write status register instruction. during this time the device will ignore further instructions except for the read status register instruction (see t w , t pp , t se , t be , and t ce in ac characteristics). when the progr am, erase or write status register instruction has completed, the busy bit will be clear ed to a 0 state indicating the device is ready for further instructions. 10.1.2 write enable latch (wel) write enable latch (wel) is a read only bit in the status register (s1) that is set to a 1 after executing a write enable instruction. the we l status bit is cleared to a 0 w hen the device is write disabled. a write disable state occurs upon power-up or after any of the following instructi ons: write disable, page program, sector erase, block erase, chip erase and write status register. 10.1.3 block protect bits (bp2, bp1, bp0) the block protect bits (bp2, bp1, and bp0) are non-volatile read/write bits in the status register (s4, s3, and s2) that provide write protection control and status. block protect bits can be set using the write status register instruction (see t w in ac characteristics). all, none or a portion of the memory array can be protected from program and erase instru ctions (see status regi ster memory protection table). the factory default setting for the block protec tion bits is 0, none of the array protected. the block protect bits can not be written to if the status register protect (srp) bit is set to 1 and the write protect (/wp) pin is low. 10.1.4 top/bottom block protect (tb) the top/bottom bit (tb) controls if the block pr otect bits (bp2, bp1, bp0 ) protect from the top (tb=0) or the bottom (tb=1) of the array as shown in the status register memory protection table. the tb bit is non-volatile and the factory default setti ng is tb=0. the tb bit can be set with the write status register instruction prov ided that the write enable instruction has been issued. the tb bit can not be written to if the status register protect (srp) bit is set to 1 and the write protect (/wp) pin is low. 10.1.5 reserved bits status register bit location s6 is reserved for fu ture use. current devices will read 0 for this bit location. it is recommended to mask out the reserved bi t when testing the status register. doing this will ensure compatibility with future devices.
w25x10a, w25x20a, w25x40a, w25x80a - 12 - 10.1.6 status register protect (srp) the status register protect (srp) bit is a non-volatile read/write bit in status register (s7) that can be used in conjunction with the write protect (/wp) pin to disable writes to status register. when the srp bit is set to a 0 state (factory default) the /wp pi n has no control over status register. when the srp pin is set to a 1, the write status register instru ction is locked out while the /wp pin is low. when the /wp pin is high the write status r egister instruction is allowed. figure 3. status register bit locations
w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 13 - revision f 10.1.7 status register memory protection status register (1) w25x80a (8m-bit) memory protection tb bp2 bp1 bp0 block(s) addresses density portion x 0 0 0 none none none none 0 0 0 1 15 0f0000h - 0fffffh 64kb upper 1/16 0 0 1 0 14 and 15 0e0000h - 0fffffh 128kb upper 1/8 0 0 1 1 12 thru 15 0c0000h - 0fffffh 256kb upper 1/4 0 1 0 0 8 thru 15 080000h - 0fffffh 512kb upper 1/2 1 0 0 1 0 000000h - 00ffffh 64kb lower 1/16 1 0 1 0 0 and 1 000000h - 01ffffh 128kb lower 1/8 1 0 1 1 0 thru 3 000000h - 03ffffh 256kb lower 1/4 1 1 0 0 0 thru 7 000000h - 07ffffh 512kb lower 1/2 x 1 0 1 0 thru 15 000000h - 0fffffh 1mb all x 1 1 x 0 thru 15 000000h - 0fffffh 1mb all status register (1) w25x40a (4m-bit) memory protection tb bp2 bp1 bp0 block(s) addresses density portion x 0 0 0 none none none none 0 0 0 1 7 070000h - 07ffffh 64kb upper 1/8 0 0 1 0 6 and 7 060000h - 07ffffh 128kb upper 1/4 0 0 1 1 4 thru 7 040000h - 07ffffh 256kb upper 1/2 1 0 0 1 0 000000h - 00ffffh 64kb lower 1/8 1 0 1 0 0 and 1 000000h - 01ffffh 128kb lower 1/4 1 0 1 1 0 thru 3 000000h - 03ffffh 256kb lower 1/2 x 1 x x 0 thru 7 000000h - 07ffffh 512kb all status register (1) w25x20a (2m-bit) memory protection tb bp2 bp1 bp0 block(s) addresses density portion x x 0 0 none none none none 0 x 0 1 3 030000h - 03ffffh 64kb upper 1/4 0 x 1 0 2 and 3 020000h - 03ffffh 128kb upper 1/2 1 x 0 1 0 000000h - 00ffffh 64kb lower 1/4 1 x 1 0 0 and 1 000000h - 01ffffh 128kb lower 1/2 x x 1 1 0 thru 3 000000h - 03ffffh 256kb all status register (1) w25x10a (1m-bit) memory protection tb bp2 bp1 bp0 block(s) addresses density portion x x 0 0 none none none none 0 x 0 1 1 010000h - 01ffffh 64kb upper 1/2 1 x 0 1 0 000000h - 00ffffh 64kb lower 1/2 x x 1 x 0 and 1 000000h - 01ffffh 128kb all note: x = don?t care
w25x10a, w25x20a, w25x40a, w25x80a - 14 - 10.2 instructions the instruction set of the w25x10a/20a/40a/80a consists of fifteen bas ic instructions that are fully controlled through the spi bus (see instruction set t able). instructions are initiated with the falling edge of chip select (/cs). the firs t byte of data clocked into the di o input provides the instruction code. data on the dio input is sampled on the rising edge of clock with most significant bit (msb) first. instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don?t care), and in some ca ses, a combination. inst ructions are completed with the rising edge of edge /cs. clock relative ti ming diagrams for each instruction are included in figures 4 through 19. all read instructions can be completed after any clocked bit. however, all instructions that write, program or erase must complete on a byte boundary (cs driven high after a full 8-bits have been clocked) otherwise the instructi on will be terminated. this feature further protects the device from inadvertent writes . additionally, while the memory is being programmed or erased, or when the status register is being written, all inst ructions except for read status register will be ignored until the program or erase cycle has completed. 10.2.1 manufacturer and device identification manufacturer id (m7-m0) winbond serial flash efh device id (id7-id0) (id15-id0) instruction abh, 90h 9fh w25x10a 10h 3011h w25x20a 11h 3012h w25x40a 12h 3013h w25x80a 13h 3014h
w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 15 - revision f 10.2.2 instruction set (1) instruction name byte 1 code byte 2 byte 3 byte 4 byte 5 byte 6 n-bytes write enable 06h write disable 04h read status register 05h (s7?s0) (1) (2) write status register 01h s7?s0 read data 03h a23?a16 a15?a8 a7?a0 (d7?d0) (next byte) continuous fast read 0bh a23?a16 a15?a8 a7?a0 dummy (d7?d0) (next byte) continuous fast read dual output 3bh a23?a16 a15?a8 a7?a0 dummy i/o = (d6,d4,d2,d0) o = (d7,d5,d3,d1) (one byte per 4 clocks, continuous) page program 02h a23?a16 a15?a8 a7?a0 (d7?d0) (next byte) up to 256 bytes block erase (64kb) d8h a23?a16 a15?a8 a7?a0 sector erase (4kb) 20h a23?a16 a15?a8 a7?a0 chip erase c7h/60h power-down b9h release power- down / device id abh dummy dummy dummy (id7-id0) (4) manufacturer/ device id (3) 90h dummy dummy 00h (m7-m0) (id7-id0) jedec id 9fh (m7-m0) manufacturer (id15- id8) memory type (id7-id0) capacity notes: 1. data bytes are shifted with most si gnificant bit first. byte fields with data in parenthesis ?( )? indicate data being read from the devic e on the do pin. 2. the status register content s will repeat continuously until /c s terminates the instruction. 3. see manufacturer and device identification table for device id information. 4. the device id will repeat continuously until /cs terminates the instruction.
w25x10a, w25x20a, w25x40a, w25x80a - 16 - 10.2.3 write enable (06h) the write enable instruction (figure 4) sets the write enable latch (wel) bit in the status register to a 1. the wel bit must be set prior to every page program, sector erase, block erase, chip erase and write status register instruct ion. the write enable instruction is entered by driving /cs low, shifting the instruction code ?06h? into the data input (di) pin on the rising edge of clk, and then driving /cs high. figure 4. write enable instruction sequence diagram 10.2.4 write disable (04h) the write disable instruction (figure 5) resets the write enable latch (wel) bit in the status register to a 0. the write disable inst ruction is entered by driving /cs low, shifting the instruction code ?04h? into the dio pin and then driving /cs high. note that the wel bit is automatically reset after power-up and upon completion of the write status register, page program, sector erase, block erase and chip erase instructions. figure 5. write disable in struction sequence diagram
w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 17 - revision f 10.2.5 read status register (05h) the read status register instructi on allows the 8-bit status register to be read. the instruction is entered by driving /cs low and shifting the instructi on code ?05h? into the dio pin on the rising edge of clk. the status register bits are then shifted out on the do pin at the falling edge of clk with most significant bit (msb) first as shown in figure 6. the status register bits are shown in figure 3 and include the busy, wel, bp2-bp0, tb and srp bits (s ee description of the status register earlier in this datasheet). the status register instruction may be used at any time, even while a program, erase or write status register cycle is in progress. this allows the busy status bit to be checked to determine when the cycle is complete and if the device can accept anot her instruction. the stat us register can be read continuously, as shown in figure 6. the inst ruction is completed by driving /cs high. figure 6. read status register instruction sequence diagram
w25x10a, w25x20a, w25x40a, w25x80a - 18 - 10.2.6 write status register (01h) the write status register instruction allows t he status register to be written. a write enable instruction must previously have been executed for the device to accept the write status register instruction (status register bit wel must equal 1) . once write enabled, the in struction is entered by driving /cs low, sending the instruction code ?01h?, and then writing the status register data byte as illustrated in figure 7. the status register bits are shown in figure 3 and described earlier in this datasheet. only non-volatile status register bits srp, tb, bp2, bp1 and bp0 (bits 7, 5, 4, 3 and 2) can be written to. all other status register bit locati ons are read-only and will not be affected by the write status register instruction. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the write status register inst ruction will not be executed. after /cs is driven high, the self-timed write status register cycle will commence for a time duration of t w (see ac characteristics). while the write status register cycle is in progress, the read status regi ster instruction may still accessed to check the status of the busy bit. the busy bit is a 1 during the write status register cycle and a 0 when the cycle is finished and ready to accept ot her instructions again. after the write register cycle has finished the write enable latch (wel) bit in the status register will be cleared to 0. the write status register instru ction allows the block protect bits (tb, bp2, bp1 and bp0) to be set for protecting all, a portion, or none of the memory from erase and program instructions. protected areas become read-only (see status register memory protection table). the write status register instruction also allows the status register protect bit (srp) to be set. this bit is used in conjunction with the write protect (/wp) pin to disable writes to the status register. when the srp bit is set to a 0 state (factory default) the /wp pin has no control over the status regi ster. when the srp pin is set to a 1, the write status register inst ruction is locked out while the /wp pin is low. when the /wp pin is high the write status register instruction is allowed. figure 7. write status register instruction sequence diagram
w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 19 - revision f 10.2.7 read data (03h) the read data instruction allows one more data by tes to be sequentially read from the memory. the instruction is initiated by driving the /cs pin lo w and then shifting the instruction code ?03h? followed by a 24-bit address (a23-a0) into the dio pin. the code and address bits are latched on the rising edge of the clk pin. after the address is received, the data byte of the addressed memory location will be shifted out on the do pin at the falling edge of clk with most significant bit (msb) first. the address is automatically incremented to the next higher address after eac h byte of data is shifted out allowing for a continuous stream of data. this m eans that the entire memory can be accessed with a single instruction as long as the clock continues. the instruction is co mpleted by driving /cs high. the read data instruction sequence is shown in figure 8. if a read data instruction is issued while an erase, program or write cycle is in process (bu sy=1) the instruction is ignored and will not have any effects on the current cycle. the r ead data instruction allows clock rates from d.c. to a maximum of f r (see ac electrical characteristics). figure 8. read data instruction sequence diagram
w25x10a, w25x20a, w25x40a, w25x80a - 20 - 10.2.8 fast read (0bh) the fast read instruction is similar to the read data instruction except t hat it can operate at the highest possible frequency of f r (see ac electrical characterist ics). this is accomplished by adding eight ?dummy? clocks after the 24-bit address as shown in figure 9. the dummy clocks allow the devices internal circuits additional time for setti ng up the initial address. during the dummy clocks the data value on the dio pin is a ?don?t care?. figure 9. fast read instruction sequence diagram
w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 21 - revision f 10.2.9 fast read dual output (3bh) the fast read dual output (3bh) instruction is similar to the standard fast read (0bh) instruction except that data is output on two pins, do and dio, instead of just do. this allows data to be transferred from the w25x10a/20a/40a/80a at twice the rate of standard spi devices. the fast read dual output instruction is ideal for quickly dow nloading code from flash to ram upon power-up or for applications that cache code-segm ents to ram for execution. similar to the fast read instructi on, the fast read dual output in struction can operate at the highest possible frequency of f r (see ac electrical characteristics) . this is accomplished by adding eight ?dummy? clocks after the 24-bit address as shown in figure 10. the dummy clocks allow the device's internal circuits additional time for setting up the initial address. the input data during the dummy clocks is ?don?t care?. however, the dio pin s hould be high-impedance prior to the falling edge of the first data out clock. figure 10. fast read dual output instruction sequence diagram
w25x10a, w25x20a, w25x40a, w25x80a - 22 - 10.2.10 page program (02h) the page program instruction allows up to 256 byte s of data to be programmed at previously erased to all 1s (ffh) memory locations. a write enable instruction must be exec uted before the device will accept the page program instruction (status regi ster bit wel must equal 1). the instruction is initiated by driving the /cs pin low then shifting the instruction code ?02h? followed by a 24-bit address (a23-a0) and at least one data byte, into the dio pin. the /cs pin must be held low for the entire length of the instruction while dat a is being sent to the device. if an entire 256 byte page is to be programmed, the la st address byte (the 8 least significant address bits) should be set to 0. if the last address byte is not zero, and the number of clocks exceed the remaining page length, the addressing will wrap to the beginning of the page. in some cases, less than 256 bytes (a partial page) can be programmed wit hout having any effect on other bytes within the same page. one condition to perform a partial page program is that the number of clocks can not exceed the remaining page length. if more than 256 by tes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. as with the write and erase instructions, the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the page pr ogram instruction will not be executed. after /cs is driven high, the self-timed page program instruction will commence for a time duration of tpp (see ac characteristics). while the page program cycle is in progress, the read status register instruction may still be accessed for checking the st atus of the busy bit. the busy bit is a 1 during the page program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after t he page program cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the p age program instruction w ill not be executed if the addressed page is protected by the block protect (bp2, bp1, and bp0) bits (see status register memory protection table). figure 11. page program instruction sequence diagram
w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 23 - revision f 10.2.11 sector erase (20h) the sector erase instruction sets all memory within a specified sector (4k-bytes) to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the sector erase instruction (status register bit wel must equal 1). the instructi on is initiated by driving the /cs pin low and shifting the instruction code ?20h? fo llowed a 24-bit sector address (a23-a0) (see figure 2). the sector erase instructi on sequence is shown in figure 12. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the sector erase instruction w ill not be executed. after /cs is dr iven high, the self-timed sector erase instruction will commence for a time duration of t se (see ac characteristics). while the sector erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 duri ng the sector erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the sector erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the sector erase instruction will not be exec uted if the addressed page is protec ted by the block protect (tb, bp2, bp1, and bp0) bits (see status r egister memory protection table). figure 12. sector erase instruction sequence diagram
w25x10a, w25x20a, w25x40a, w25x80a - 24 - 10.2.12 block erase (d8h) the block erase instruction sets all memory within a specified block (64k-bytes ) to the erased state of all 1s (ffh). a write enable instruction must be executed before the devic e will accept the block erase instruction (status register bit wel must equal 1). the instructi on is initiated by driving the /cs pin low and shifting the instruction code ?d8h? fo llowed a 24-bit block address (a23-a0) (see figure 2). the block erase instruction sequence is shown in figure 13. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase instruction will not be executed. after /cs is driven high, the self-timed block erase instruction will commence for a time duration of t be (see ac characteristics). while the block erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 duri ng the block erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept ot her instructions again. a fter the block erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase instruction will not be executed if the addressed page is protected by the block protect (tb, bp2, bp1, and bp0) bits (see status regist er memory protection table). figure 13. block erase instruction sequence diagram
w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 25 - revision f 10.2.13 chip erase (c7h or 60h) the chip erase instruction sets all memory within the device to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the chip erase instruction (status register bit wel must equal 1). the instru ction is initiated by driving the /cs pin low and shifting the instruction code ?c7h? or ?60h?. the ch ip erase instruction sequence is shown in figure 14. the /cs pin must be driven high after the eighth bit has been latched. if this is not done the chip erase instruction will not be executed. after /cs is driven high, the self-timed chip erase instruction will commence for a time duration of t ce (see ac characteristics). while the chip erase cycle is in progress, the read status register instruction may still be accessed to check the status of the busy bit. the busy bit is a 1 during the chip erase cy cle and becomes a 0 when finished and the device is ready to accept other instructi ons again. after the chip erase cy cle has finished the write enable latch (wel) bit in the status register is cleared to 0. the chip erase instruction will not be executed if any page is protected by the block protect (bp2 , bp1, and bp0) bits (see status register memory protection table). figure 14. chip erase instruction sequence diagram
w25x10a, w25x20a, w25x40a, w25x80a - 26 - 10.2.14 power-down (b9h) although the standby current during nor mal operation is relatively low, standby current can be further reduced with the power-down instruction. the lower power consumption makes the power-down instruction especially useful for battery pow ered applications (see icc1 and icc2 in ac characteristics). the instruction is initiated by driving the /cs pin low and shifting the instruction code ?b9h? as shown in figure 15. the /cs pin must be driven high after the eighth bit has been latched. if this is not done the power- down instruction will not be executed. after /cs is driven high, the power-down state will entered within the time duration of t dp (see ac characteristics). while in the power-down state only the release from power-down / device id instruction, which restores the device to normal operation, will be recognized. all other instructions are ignored. this includes the r ead status register instruction, which is always available during normal operation. ignoring all but one instruction makes the power down state a useful condition for securing maximum write protection. the device always powers-up in the normal operation with t he standby current of icc1. figure 15. deep power-down instruction sequence diagram
w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 27 - revision f 10.2.15 release power-down / device id (abh) the release from power-down / device id instructi on is a multi-purpose instruction. it can be used to release the device from the power- down state, obtain the devices electronic identification (id) number or do both. when used only to release the device from the power- down state, the instructi on is issued by driving the /cs pin low, shifting the instruction code ?abh ? and driving /cs high as shown in figure 16. after the time duration of t res1 (see ac characteristics) the device will resume normal operation and other instructions will be accepted. the /cs pin must remain high during the t res1 time duration. when used only to obtain the device id while not in the power-down state, the instruction is initiated by driving the /cs pin low and shifting the instru ction code ?abh? followed by 3-dummy bytes. the device id bits are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 17. the device id values fo r the w25x10a, w25x20a, w25x40a and w25x80a are listed in manufacturer and device identification t able. the device id can be read continuously. the instruction is completed by driving /cs high. when used to release the device from the power-dow n state and obtain the device id, the instruction is the same as previously described, and shown in figure 17, except that after /cs is driven high it must remain high for a time duration of t res2 (see ac characteristics). after this time duration the device will resume normal operation and other instructions will be accepted. if the release from power-down / device id instru ction is issued while an erase, program or write cycle is in process (when busy equals 1) the inst ruction is ignored and will not have any effects on the current cycle figure 16. release power-down instruction sequence
w25x10a, w25x20a, w25x40a, w25x80a - 28 - figure 17. release power-down / devi ce id instruction sequence diagram
w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 29 - revision f 10.2.16 read manufacturer / device id (90h) the read manufacturer/device id instruction is an alternative to the release from power-down/ device id instruction that prov ides both jedec assigned manufacturer id and the specific device id. the read manufacturer/device id instruction is very similar to the release from power-down / device id instruction. the instruction is initiated by driving the /cs pin low and shifting the instruction code ?90h? followed by a 24-bit address (a23-a0) of 000000h. after which, the manufacturer id for winbond (efh) and the device id are shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 18. the device id values for the w25x10a, w25x20a, w25x40a and w25x80a are listed in manufacturer and device identification table. if the 24-bit address is initially set to 000001h the device id will be read first and then follo wed by the manufacturer id. the manufacturer and device ids can be read continuously, alternati ng from one to the other. the instruction is completed by driving /cs high. figure 18. read manufacturer / device id diagram
w25x10a, w25x20a, w25x40a, w25x80a - 30 - 10.2.17 jedec id (9fh) for compatibility reasons, the w25x10a /20a/40a/80a provides several instructions to electronically determine the identity of the device. the read jedec id instruction is compatible with the jedec standard for spi compatible serial memories that was adopted in 2003. the instruction is initiated by driving the /cs pin low and shifting the instruction code ?9fh?. the jedec assigned manufacturer id byte for winbond (e fh) and two device id bytes, memory type (id15-id8) and capacity (id7-id0) are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 19. for memory type and capacity values refer to manufacturer and device identification table. figure 19. read jedec id
w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 31 - revision f 11. electrical characteristics 11.1 absolute maximum ratings (1) parameters symbol conditions range unit supply voltage vcc ?0.6 to +4.0 v voltage applied to any pin v io relative to ground ?0.6 to vcc +0.4 v transient voltage on any pin v iot <20ns transient relative to ground ?2.0v to vcc+2.0v v storage temperature t stg ?65 to +150 c lead temperature t lead see note (2) c electrostatic discharge voltage v esd human body model (3) ?2000 to +2000 v notes: 1. the device has been designed and tested for the specified operation ranges. proper operation outside of these levels is not guaranteed. exposure to absolute maxi mum ratings may affect device reliability. exposure beyond absolute maxi mum ratings may cause permanent damage. 2. compliant with jedec standard j-std-20c for small body sn-pb or pb-free (green) assembly and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. 3. jedec std jesd22-a114a (c1= 100 pf, r1=1500 ohms, r2=500 ohms). 11.2 operating ranges spec parameter symbol conditions min max unit supply voltage (1) vcc f r0 = 75mhz, f r = 50mhz f r1 = 100mhz, f r = 50mhz 2.7 3.0 3.6 3.6 v ambient temperature, operating t a commercial (2) industrial 0 ?40 +70 +85 c note: 1. vcc voltage during read can operate across the min and max range but should not exceed 10% of the programming (erase/write) voltage. 2. commercial temperature only applies to fast read (f r1 ) and 100k cycles endurance for 4k byte sectors . industrial temperature applies to all other parameters. 11.3 power-up timing and write inhibit threshold
w25x10a, w25x20a, w25x40a, w25x80a - 32 - spec parameter symbol min max unit vcc (min) to /cs low t vsl (1) 10 s time delay before write instruction t puw (1) 1 10 ms write inhibit threshold voltage v wi (1) 1 2 v note: 1. these parameters are characterized only. figure 20. power-up timing and voltage levels
w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 33 - revision f 11.4 dc electrical characteristics spec parameter symbol conditions min typ max unit input capacitance c in (1) v in = 0v (2) 6 pf output capacitance cout (1) v out = 0v (2) 8 pf input leakage i li 2 a i/o leakage i lo 2 a standby current i cc 1 /cs = vcc, vin = gnd or vcc 25 50 a power-down current i cc 2 /cs = vcc, vin = gnd or vcc <1 10 a current read data / dual output 1mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 4/5 6/7.5 ma current read data / dual output 33mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 6/7 9/10 ma current read data / dual output 50mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 7/8 10/12 ma current read data / dual output 75mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 10/11 15/16.5 ma current read data / dual output 100mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 12/13 17/18 ma current page program i cc 4 /cs = vcc 20 25 ma current write status register i cc 5 /cs = vcc 8 12 ma current sector/block erase i cc 6 /cs = vcc 20 25 ma current chip erase i cc 7 /cs = vcc 20 25 ma input low voltage v il ?0.5 vccx0.3 v input high voltage v ih vccx0.7 vcc+0.4 v output low voltage v ol i ol = 1.6 ma 0.4 v output high voltage v oh i oh = ?100 a vcc?0.2 v notes: 1. tested on sample basis and specified through design and characterization dat a. ta=25c, vcc=3v. 2. checker board pattern.
w25x10a, w25x20a, w25x40a, w25x80a - 34 - 11.5 ac measurement conditions spec parameter symbol min max unit load capacitance load capacitance for f r1 only c l 30 15 pf input rise and fall times t r , t f 5 ns input pulse voltages v in 0.2 vcc to 0.8 vcc v input timing reference voltages in 0.3 vcc to 0.7 vcc v output timing reference voltages o ut 0.5 vcc to 0.5 vcc v note: 1. output hi-z is defined as the point where data out is no longer driven. figure 21. ac measurement i/o waveform
w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 35 - revision f 11.6 ac electrical characteristics spec description symbol alt min typ max unit clock frequency for all instructions, except read data (03h) 2.7v-3.6v vcc & industrial temperature f r0 f c0 d.c. 75 mhz clock frequency, for fast read (0bh, 3bh) only 3.0v-3.6v vcc & commercial temperature f r1 (4) f c1 d.c. 100 mhz clock freq. read data instruction 03h f r d.c. 50 mhz clock high, low time, for fast read (0bh, 3bh) / other instructions except read data (03h) t clh , t cll (1) 4.5 ns clock high, low time for read data (03h) instruction t crlh , t crll (1) 8 ns clock rise time peak to peak t clch (2) 0.1 v/ns clock fall time peak to peak t chcl (2) 0.1 v/ns /cs active setup time relative to clk t slch t css 5 ns /cs not active hold time relative to clk t chsl 5 ns data in setup time t dvch t dsu 2 ns data in hold time t chdx t dh 5 ns /cs active hold time relative to clk t chsh 5 ns /cs not active setup time relative to clk t shch 5 ns /cs deselect time (for array read ? array read / erase or program ? read status register) t shsl t csh 50/100 ns output disable time t shqz (2) t dis 7 ns clock low to output valid t clqv t v 6 ns output hold time t clqx t ho 0 ns continued ? next page
w25x10a, w25x20a, w25x40a, w25x80a - 36 - 11.7 ac electrical characteristics ( cont?d) spec description symbol alt min typ max unit /hold active setup time relative to clk t hlch 5 ns /hold active hold time relative to clk t chhh 5 ns /hold not active setup time relative to clk t hhch 5 ns /hold not active hold time relative to clk t chhl 5 ns /hold to output low-z t hhqx (2) t lz 7 ns /hold to output high-z t hlqz (2) t hz 12 ns write protect setup time before /cs low t whsl (3) 20 ns write protect hold time after /cs high t shwl (3) 100 ns /cs high to power-down mode t dp (2) 3 s /cs high to standby mode without electronic signature read t res 1 (2) 3 s /cs high to standby mode with electronic signature read t res 2 (2) 1.8 s write status register time t w 10 15 ms byte program time (first byte) (5) t bp1 30 50 s additional byte program time (after first byte) (5) t bp2 6 12 s page program time t pp 1.5 3 ms sector erase time (4kb) t se 120 250 ms block erase time (64kb) t be 0.4 1 s chip erase time w25x10a / w25x20a chip erase time w25x40a chip erase time w25x80a t ce 1.5 3 6 3 5 10 s s s notes: 1. clock high + clock low must be less than or equal to 1/f c . 2. value guaranteed by design and/or characte rization, not 100% tested in production. 3. only applicable as a constraint for a write status register instruction when sector protect bit is set to 1. 4. commercial temperature only applies to fast read (f r1 ). industrial temperature applie s to all other parameters. 5. for multiple bytes after first byte within a page, t bpn = t bp1 + t bp2 * n (typical) and t bpn = t bp1 + t bp2 * n (max), where n = number of bytes programmed .
w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 37 - revision f 11.8 serial output timing 11.9 input timing 11.10 hold timing
w25x10a, w25x20a, w25x40a, w25x80a - 38 - 12. package specification 12.1 8-pin soic 150-mil (package code sn) l o c d a1 a e b seating plane y 0.25 gauge plane e h e 1 8 5 4 millimeters inches symbol min max min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.008 0.010 e (3) 3.80 4.00 0.150 0.157 d (3) 4.80 5.00 0.188 0.196 e (2) 1.27 bsc 0.050 bsc h e 5.80 6.20 0.228 0.244 y (4) - 0.10 - 0.004 l 0.40 1.27 0.016 0.050 t 0 10 0 10 notes: 1. controlling dimensions: millimeter s, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e do not include mold flash protrusi ons and should be measured from the bottom of the package. 4. formed leads coplanarity with respect to seating plane shall be within 0.004 inches.
w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 39 - revision f 12.2 8-pin soic 208-mil (package code ss) millimeters inches symbol min nom max min nom max a 1.75 1.95 2.16 0.069 0.077 0.085 a1 0.05 0.15 0.25 0.002 0.006 0.010 a2 1.70 1.80 1.91 0.067 0.071 0.075 b 0.35 0.42 0.48 0.014 0.017 0.019 c 0.19 0.20 0.25 0.007 0.008 0.010 d 5.18 5.28 5.38 0.204 0.208 0.212 d1 5.13 5.23 5.33 0.202 0.206 0.210 e 5.18 5.28 5.38 0.204 0.208 0.212 e1 5.13 5.23 5.33 0.202 0.206 0.210 e 1.27 bsc 0.050 bsc h 7.70 7.90 8.10 0.303 0.311 0.319 l 0.50 0.65 0.80 0.020 0.026 0.031 y - - 0.010 - - 0.004 0 - 8 0 - 8 notes: 1. controlling dimensions: millimeter s, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d1 and e1 do not include mold flash protrusions and should be meas ured from the bottom of the package. 4. formed leads coplanarity with respect to seating plane shall be within 0.004 inches.
w25x10a, w25x20a, w25x40a, w25x80a - 40 - 12.3 8-pin pdip 300-mil (package code da) seating plane e a 2 a c e base plane 1 a 1 e l a s 1 e d 1 b b 8 5 1 4 millimeters inches symbol min typ. max min typ. max a --- --- 4.45 --- --- 0.175 a1 0.25 --- --- 0.010 --- --- a2 3.18 3.30 3.43 0.125 0.130 0.135 b 0.41 0.46 0.56 0.016 0.018 0.022 b1 1.47 1.52 1.63 0.058 0.060 0.064 c 0.20 0.25 0.36 0.008 0.010 0.014 d - 9.14 9.65 - 0.360 0.380 e 7.37 7.62 7.87 0.290 0.300 0.310 e1 6.22 6.35 6.48 0.245 0.250 0.255 e1 2.29 2.54 2.79 0.090 0.100 0.110 l 3.05 3.30 3.56 0.120 0.130 0.140 0 - 15 0 - 15 e a 8.51 9.02 9.53 0.335 0.355 0.375
w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 41 - revision f 12.4 8-contact 6x5mm wson (package code zp) ? millimeters inches symbol min typ. max min typ. max a 0.70 0.75 0.80 0.0275 0.0295 0.0314 a1 0.00 0.02 0.05 0.0000 0.0007 0.0019 b 0.35 0.40 0.48 0.0137 0.0157 0.0188 c - 0.20 ref. - - 0.0078 ref. - d 5.90 6.00 6.10 0.2322 0.2362 0.2401 d2 3.35 3.40 3.45 0.1318 0.1338 0.1358 e 4.90 5.00 5.10 0.1929 0.1968 0.2007 e2 4.25 4.30 4.35 0.1673 0.1692 0.1712 e (2) 1.27 bsc 0.0500 bsc l 0.55 0.60 0.65 0.0216 0.0236 0.0255 y 0.00 - 0.75 0.0000 - 0.0029
w25x10a, w25x20a, w25x40a, w25x80a - 42 - 8-pad wson 6x5mm cont?d. millimeters inches symbol min . typ. max min typ max solder pattern m 3.40 0. 38 13 n 4.30 0. 92 16 p 6.00 0. 60 23 q 0.50 0. 96 01 r 0.75 0. 55 02 notes: 1. advanced packaging information; please contact winbond for the latest minimum and maximum specifications. 2. bsc = basic lead spacing between centers. 3. dimensions d and e do not include mold flash protrusi ons and should be measured from the bottom of the package. 4. the metal pad area on the bottom center of the package is connected to the device ground (g nd pin). avoid placement of exposed pcb vias under the pad
w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 43 - revision f 13. ordering information (1) w 25x xx a v xx (2) i = industrial (-40c to +85c) ss = 8-pin soic 208-mil da = 8-pin pdip 300-mil sn = 8-pin soic 150-mil zp = 8-pad wson 6x5mm v = 2.7v to 3.6v 10a = 1m-bit 20a = 2m-bit 40a = 4m-bit 80a = 8m-bit 25x = spiflash serial flash memory with 4kb sectors, dual outputs w = winbond (blank) standard g, z = green package (lead-free, rohs compli ant, halogen-free (tbba), anti mony-oxide-free sb2o3) notes: 1a. the winbond w25x10a, w25x20a, w25x40a and w25x80a are fully compatible with the previous winbond w25x10, w25x20, w25x40 and w25x80 se rial flash memories. 1b. standard bulk shipments are in tube (shape e). please s pecify alternate packing method, such as tape and reel (shape t), when placing orders. 1c. the ?w? prefix is not included on the part marking. 2. only the 2 nd letter is used for the part marking; wson pa ckage type zp is not used for the part marking.
w25x10a, w25x20a, w25x40a, w25x80a - 44 - 13.1 valid part numbers and top side marking the following table provides the valid part numbers for the 25x10a/20a/40a/80a spiflash memories. please contact winbond for specific availability by density and package type. winbond spiflash memories use an 12-digit product number for orderi ng. however, due to limited space, the top side marking on all packages use an abbreviated 10-digit number. package type density product number top side marking 1m-bit w25x10avsnig 25x10avnig 2m-bit w25x20avsnig 25x20avnig 4m-bit w25x40avsnig 25x40avnig sn soic-8 150mil 8m-bit w25x80avsnig (2) 25x80avnig 4m-bit w25x40avssig 25x40avsig ss soic-8 208mil 8m-bit w25x80avssig 25x80avsig 1m-bit w25x10avzpig 25x10avig 2m-bit w25x20avzpig 25x20avig 4m-bit w25x40avzpig 25x40avig zp (1) wson-8 6x5mm 8m-bit w25x80avzpig 25x80avig 4m-bit w25x40avdaiz 25x40avaiz da pdip-8 300mil 8m-bit w25x80avdaiz 25x80avaiz note: 1. for wson packages, the package type zp is not used in the top side marking. 2. package type sn (soic8 150mil) is a spec ial order package, please contact winbond for ordering information.
w25x10a, w25x20a, w25x40a, w25x80a publication release date: august 7, 2009 - 45 - revision f 14. revision history version date page description a 01/09/08 new create b 02/27/08 43 & 44 added note for wson top side marking c 05/02/08 40 updated 8-pin pdip package dimensions d 07/23/08 4, 35 & 44 updated features section updated tclqv added g option for pdip package e 11/25/08 43 & 44 updated ordering information removed g option for pdip package f 08/07/09 38~44 update package diagrams updated ordering information. trademarks winbond and spiflash are trademarks of winbond electronics corporation. all other marks are the property of their respective owner. important notice winbond products are not designed, intended, author ized or warranted for use as components in systems or equipment intended for surg ical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instrument s, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein fa ilure of winbond products could result or lead to a situation wherein personal injury, death or seve re property or environmental damage could occur. winbond customers using or selling these products for us e in such applications do so at their own risk and agree to fully indemnify winbond for any damages re sulting from such improper use or sales. information in this document is provided solely in connection with winbond products. winbond reserves the right to make changes, corrections, m odifications or improvements to this document and the products and services decribed herei n at any time, without notice.

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